The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device using a local silicon-on-insulator (LSOI) process without over etching underneath the active regions.
As dynamic random access memory (DRAM) devices have become highly integrated, active regions have shrunk accordingly. Thus, it has become difficult to pattern an active region under 80 nm, and spacing distances between active regions have decreased, which increases leakage current between cells. An attempt to reduce the leakage between cells has been made by forming a deep trench to define the isolation structure. Since the isolation structure defines the active region, the length of the current channel can be increased by increasing the depth of the isolation structure.
However, a void may be generated when a subsequent oxide-based layer is used to fill the deep trench. The deep depth of the trench makes it difficult to completely fill it without any void. Furthermore, the etching needs to be performed longer to form the deep trench so an increased mask thickness is required. The deep trench and the thick mask are more prone to collapse, which results in a decrease in yield. Accordingly, a local silicon-on-insulator (LSOI) process has been introduced to overcome the above limitations.
FIG. 1A illustrates a cross-sectional view describing a typical isolation method for a semiconductor device, using an LSOI process. Isolation regions formed in a substrate 11 are etched to form first trenches 12 having a vertical profile. Sidewall insulation layers 13 are formed on the sidewalls of the first trenches 12. The first trenches 12 define an active region 11A.
An isotropic etching process is performed on portions of the substrate 11 below the first trenches 12 to form second trenches 14 using the sidewall insulation layers 13 as protection layers. The second trenches 14 are extended horizontally underneath the active region 11A. The isotropic etching process includes performing a blanket etch-back process without using a mask. The active region 11A becomes supported by a pillar 11B having a width of ‘W1’. Although not illustrated, an isolation structure fills the isolation regions configured with the first trenches 12 and the second trenches 14 to complete an LSOI process.
FIG. 1B illustrates a top view of a semiconductor device after typical second trenches are formed. The second trenches are formed below active regions 21A and are extended horizontally. Forming the horizontally extended second trenches allows for the reduction of leakage current while not increasing the depth of the isolation regions.
However, forming the horizontally-extending second trenches using an isotropic etching process, e.g., blanket etch-back process, causes extension in both directions {circle around (1)} and {circle around (2)} The direction {circle around (1)} represents a direction toward a bit line contact region, and the direction {circle around (2)} represents a direction toward a storage node contact region. Consequently, the width of a pillar 21B decreases. That is, a sufficient pillar length ‘L’ of the active regions 21A may not be obtained, thereby causing a collapse of the active regions 21A.
FIG. 2 is a micrograph view illustrating collapsed active regions due to the insufficient pillar length of the active regions as indicated by the circled regions. The collapsed active regions may cause a decrease in yield and contamination of devices in other processes.